Brookhaven National Laboratory ASIC Design CAD Management Engineer in Upton, New York
ASIC Design CAD Management Engineer Job ID 2156 Date posted 08/30/2020
Brookhaven National Laboratory (www.bnl.gov) delivers discovery science and transformative technology to power and secure the nation's future. Brookhaven Lab is a multidisciplinary laboratory with seven Nobel Prize-winning discoveries, 37 R&D 100 Awards, and more than 70 years of pioneering research. The Lab is primarily supported by the U.S. Department Energy’s (DOE) Office of Science. Brookhaven Science Associates (BSA) operates and manages the Laboratory for DOE. BSA is a partnership between Battelle and The Research Foundation for the State University of New York on behalf of Stony Brook University.
The mission of the Instrumentation Division is to develop state-of-the-art instrumentation required for experimental research programs at Brookhaven Lab and to maintain the expertise and facilities in specialized high technology areas essential for this work. Development of facilities is motivated by present Brookhaven research programs and anticipated future directions of research. Our work has a significant impact on programs throughout the world that rely on state-of-the-art radiation detectors and readout electronics.
Are you someone who steps up to challenges and thrives on group project work in a technology R&D environment?
As an ASIC CAD Management Engineer, you will build and maintain the design infrastructure, provide tool support and training, and serve as the custodial of the CAD/EAD tools for our ASIC team. You will collaborate closely with scientists, engineers, technicians and information technology experts on complex, meaningful projects for the Lab and our institutional partners.
Our science and engineering challenges are complex and unique! We are engaged in the development of ASICs for particle detectors, high resolution X- and gamma-ray spectrometers, and high-rate photon counters and imagers. Our ASIC’s work is in extreme environments of cryogenic temperatures or withstanding extreme irradiation doses. Quantum Information Science, Machine Learning and Neuromorphic processing are where our R&D efforts go. The application and implementation of our hardware is within BNL and other international user facilities. Your work has the potential to shape the instruments for scientific discovery and engineering advancements across the globe!
Essential Duties and Responsibilities:
Build and maintain an up-to-date design environment for the ASIC team:
work with IT team for maintenance of Linux-based cluster and its configuration for running reliably CAD/EDA ASIC design tools, process design kits, repositories of design libraries, process-design kits, and storage of IP and outside-vendor libraries
install and maintain CAD/EDA design tools from major vendors, such as Cadence, Mentor, Synopsis
integrate designs in multi-user environment via process and design management tools, such as SOS Design Manager
organize work directories, system shell scripts, tool scripts, and design verification decks, procedures for efficient and secure organization of design flows
manage process and design access
Interact with major vendors for providing optimized tools-set for the team
Organize tools, process design kits and design techniques workshops and training
Introduce and monitor standardized practices within the group
Participate in ASIC designs (analog, digital and mixed-mode), upon qualifications and as necessary
Required Knowledge, Skills, and Abilities:
Bachelor's degree in an engineering discipline or closely related field of study
Minimum three (3) years related work experience
Familiarity with specificity of ASIC design processes and flows
Familiarity with CAD/EDA tools for ASIC design and their interoperability
Knowledge of operating system shell scripting or other scripting languages, such as Pearl, Python, and others
Knowledge of SKILL, Tcl/Tk, ASSURA and Calibre DRC/LVS verification decks syntax
Preferred Knowledge, Skills, and Abilities:
Master's degree in an engineering discipline or closely related field of study
Ability to execute analog and/or digital ASIC design flows for performing design tasks
Knowledge of back-end ASIC design elements, such as layout, physical verification, and design verification
Ability to provide guidance in specific areas to the ASIC team
The selected candidate will be placed at the appropriate level based on the depth and breadth of relevant engineering knowledge, skills and experience.
At Brookhaven National Laboratory we believe that a comprehensive employee benefits program is an important and meaningful part of the compensation employees receive. Our benefits program includes, but is not limited to:
Paid Parental Leave
Swimming Pool, Weight Room, Tennis Courts, and many other employee perks and benefits
Brookhaven National Laboratory (BNL) is an equal opportunity employer that values inclusion and diversity at our Lab.We are committed to ensuring that all qualified applicants receive consideration for employment and will not be discriminated against on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, age, status as a veteran, disability or any other federal, state or local protected class.
BNL takes affirmative action in support of its policy and to advance in employment individuals who are minorities, women, protected veterans, and individuals with disabilities.We ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment.Please contact us to request accommodation.
*VEVRAA Federal Contractor
Brookhaven employees are subject to restrictions related to participation in Foreign Government Talent Recruitment Programs, as defined and detailed in United States Department of Energy Order 486.1. You will be asked to disclose any such participation at the time of hire for review by Brookhaven. The full text of the Order may be found at: